Samsung Electronics has previously released the 3 Nanometer Foundry process by 2020. According to the analysis, the design cost of 3 Nanometer Foundry process chip will be as high as 1 billion 500 million US dollars. Although the increase in the cost of chip design is very high, according to experts, it is said that the current efficiency and the performance increase range are not proportional to the cost, and considering the high cost, the number of enterprises that can design 3 nanoscale projects can be counted.

In July 17th, International Business Strategy (IBS), a semiconductor regulator, said that the cost of chip design for 3 nanoscale chips would be as high as 400 million to 1 billion 500 million dollars. IBS shows that the design cost of GPU is the highest with relatively high design complexity. The company's data shows that the average design cost for 28 nanoscale chips is $5130, while the cost of designing 7 nanoscale chips using FinFET technology is $297 million 800 thousand, which is nearly 6 times the increase. The design cost of semiconductor chips includes IP, Architecture, inspection, physical verification, software, trial production and so on.

This is also the reason why the Fabless factory in the semiconductor industry has always favored the 16 nanometer FinFET and Samsung's 14 nm FinFET process. For Foundry manufacturers, the cost is also very troublesome, not only the 3 Nanometer process is also very difficult.

The 3 Nanometer process of Samsung Electronics will use GAAE (Gate-All-AroundEarly), GAAP (Gate-All-Around Plus) technology for the first time, and is named MBCFET (MultiBridge Channel FET). The core of the technology is to ensure the current of each Gate channel exists. If the FinFET structure is a 3 side current, all surfaces of GAA Gate must be ensured that the current is increased, and the performance of the current channel will increase as well.

Samsung Electronics's MBCFET technology is jointly developed by IBM and GF of the United States. If FinFET is vertically arranged in a fish like Gate, GAA is a transverse stacking arrangement of Gate. In order to produce this Gate structure, a series of innovations such as Pattern development, evaporation and etching are needed. In order to reduce the parasitic capacitance, new materials such as cobalt and ruthenium substitute for copper are also introduced.

According to the industry, 3 Nano Engineering Development and chip design are feasible under the support of huge financial resources, but the key is whether it is worth investing so much. And there are only a few companies that can use such projects, such as Qualcomm, apple, NVIDIA, apple and so on, which will also be a stumbling block for the 3 Nanometer project.